1. Field of the Invention
The present invention generally relates to a high/low voltage tolerant interface circuit, and more particularly, to an interface circuit that uses the bulk voltage of a control transistor to increase the reliability of gate oxide layers and a crystal oscillator using the same.
2. Description of Related Art
In recent years, complementary metal oxide semiconductor (CMOS) technology has played an increasingly important role in the circuit industry around the world. With rapid progress in nanometer-scale processing techniques, the circuit design of a chip can be realized using transistors with a smaller dimension so as to reduce chip area and lower the fabrication cost of the chip. As a result, the voltage of a power supply for powering the chip can be lowered to about 1V in order to reduce power consumption.
However, some of the peripheral devices or integrated circuits of micro-electronic systems still operate at a high voltage in order to be compatible to an earlier interface specification. When a chip using a low power supply voltage and the peripheral devices or integrated circuits are simultaneously operated, an interface circuit between the two is needed to process input and output signals that have different voltages.
A complete input and output library comprises digital and analog input and output cells, system voltage and ground voltage cells and crystal oscillator cells. In related prior art, only the design of mixed voltage input and output circuits have been considered. However, no one has yet proposed an application of the mixed voltage design to a crystal oscillator circuit. If a crystal oscillator circuit that uses a low voltage device is applied to an interface circuit having mixed voltages, then the higher input voltage can probably punch through the gate oxide layer of the transistors of the crystal oscillator circuit.
FIG. 1A is a diagram of a part of a conventional pierce-type crystal oscillator circuit. As shown in FIG. 1A, the crystal 102 is coupled between an input bonding pad X1 and an output bonding pad XO for generating a stable clock signal to an integrated circuit 100 to make it operate. An inverter amplifier 101 is normally integrated to the integrated circuit 100 for providing a voltage gain and a 180° phase-shifted signal.
The two ends of the crystal 102 are coupled to capacitors C1 and C2, respectively. The capacitors C1 and C2 stabilize the frequency of the clock signal and provide a means of routing the 180° phase-shifted signal to a feedback path. A resistor Rf is used to apply an bias of about half of the power supply voltage to the inverter amplifier 101 so as to operate the inverter amplifier 101 in a high-gain linear region.
Although the oscillation of the crystal 102 can generate a clock signal to provide the integrated circuit 100, other external clock can be used as a source of the clock signal required by the integrated circuit 100. In addition, the external clock signal can be transmitted to the integrated circuit 100 through the input bonding pad X1 while the output bonding pad XO is floating.
FIG. 1B is a diagram of a conventional crystal oscillator circuit having low voltage devices. The low voltage devices are devices that operate at a one time the system voltage (1×VDD). As shown in FIG. 1B, P-type transistors P1˜P2 and N-type transistors N1˜N2 form an inverter amplifier 101. When the crystal 102 is coupled between the input bonding pad X1 and the output bonding pad XO, the capacitors C1 and C2, which are coupled to the two ends of the crystal 102, can convert the oscillation signal generated by the crystal 102 into a sine wave signal. Through an inverter 103 formed by the combination of a P-type transistor P3 and an N-type transistor P4, the sine wave signal is converted to a square wave clock signal and the square wave clock signal is output to the integrated circuit 100 through a node XC.
When the clock signal of the integrated circuit 100 is provided by an external source, the external clock signal is received through the input bonding pad X1. If the highest operating voltage of the enable signal EN is a one time the system voltage (1×VDD) but the highest operating voltage of the external clock signal input from the input bonding pad X1 is a two-time system voltage (2×VDD), then the gate oxide layer of the P-type transistor P1 and the N-type transistor N2 can be damaged through a high voltage. The signal EN is controlled by the integrated circuit 100.
To resolve the gate oxide reliability problem, the P-type transistor P1 and the N-type transistor N1 can be switched to thick-oxide transistors. However, the circuit of the chip needs to have both thick-oxide and thin-oxide devices and the fabrication cost of the chip might be substantially increased.